A4000 Accelerators

ID #3080

GVP (Great Valley Products): A4060/T-Rex-II


Connection: CPU Fast Slot (A3000/A4000)

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Processor:060@50Mhz
FPU:Internal
MMU:Internal
Max Ram:128MB
Ram Type:4 x 72pin SIMM slots.

An accelerator which plugs into the CPU Fast slot. It also includes an onboard SCSI controller (Symbios Logic 53C710) with a 50pin internal connector.

Jumpers

JumperFunction
JP1CPU Select
ON=68060
OFF = Motherboard Processor
JP2RESERVED
JP4Cache Burst to A4000 Motherboard
ON = Enabled
OFF = Disabled
JP5Interrupt Pending, DMA Backoffs
ON = DMA Backsoff Interrup
OFF = DMA Ignores Interrupt
JP6Active SCSI Termination
ON = SCSI Termination Disabled
OFF= SCSI Termination Enabled
JP7CPU Clock Disable (Test Only)
ON = Clock Disabled
OFF = Clock Enabled
JP8CPU Clock
Pins 1 and 2 = 68040
Pins 2 and 3 = 68060
JP9CPU Power
Pins 1 and 2 = 5V (040)
Pins 2 and 3 = 3.3V (060)
CN65V Fan
CN8SCSI LED Indicator
JR1Memory Burst Mode
ON = Burst Mode Support (Min 2 SIMMs Required)
OFF = Non Burst Mode
JR2DRAM Speed versus CPU Clock OFF
@ 50 Mhz OFF = 60ns
@ 50Mhz ON = 70ns
@ 40Mhz OFF = 60/70ns
@40Mhz ON = 80ns
@ 33Mhz OFF = 60/70/80ns
JR3Burst Write Enabled
ON = Write Enabled
JR4Burst Read Enabled
ON = Read Enabled
JR5Memory Size
ON = 16MB
OFF = 4MB
JR6SIMM Type
OFF = Single Sided
ON = Double Sided
JR7Reserved
JR8Refresh Mode
OFF/ON = 4k Refresh (Asymmetrical)
OFF = 2k (Symmetrical)

All four SIMM sockets can support either 4MB or 16MB single sided SIMMs or 8MB or 32MB double sided SIMMs, depending on the settings of JR5 and JR6 as shown below

JR5 OFF, JR6 OFF
CN1 8000000-83FFFFF
CN2 8400000-87FFFFF
CN3 8800000-8BFFFFF
CN4 8C00000-8FFFFFF

JR5 OFF, JR6 OFF
CN1 8000000-8FFFFFF
CN2 9000000-9FFFFFF
CN3 A000000-AFFFFFF
CN4 B000000-BFFFFFF

JR5 OFF, JR6 ON
CN1 8000000-8FFFFFF
CN2 8800000-8FFFFFF
CN3 9000000-97FFFFF
CN4 9800000-9FFFFFF

JR5 ON, JR6 ON
CN1 8000000-9FFFFFF
CN2 A000000-BFFFFFF
CN3 C000000-DFFFFFF
CN4 E000000-FFFFFFF

Note: Burst Mode will only function properly when there are an even number of SIMMS

Trex-II Support Site

Contributions to this page by:
Mark Smith, Michael Mellendorf

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Last update: 2009-01-25 12:42
Revision: 1.0

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